1. Field of the Invention
The present invention relates generally to a method of fabricating semiconductor devices, and more particularly, to a method of fabricating semiconductor devices capable of maintaining contact hole of fine size when the contact hole for bit line formation is defined.
2. Description of the Related Art
As is generally known, contact holes are employed as connection paths for electrically connected semiconductor devices and act as wiring or upper and lower wiring. Conventionally, the wiring is formed by filling metal into the contact hole.
However, as semiconductor devices become highly integrated, the size of the contact hole necessarily must be decreased. Therefore, recent efforts are focused on decreasing the size of the contact hole.
FIGS. 1A to 1D are cross sectional views for showing the steps of a conventional method for fabricating semiconductor devices and FIG. 2 is a TEM photograph of the structure shown in FIG. 1C.
Referring to FIG. 1A, oxidized silicon is deposited on a semiconductor substrate 100 including a transistor in accordance with a Chemical Vapor Deposition (hereinafter, referred to as CVD) process, thereby forming an insulating layer 104. Then, an Organic Bottom Anti-Reflective Coating layer 106 is formed on the insulating layer 104. The Anti-Reflective Coating layer 106 prevents reflection of exposed light in the following exposure process.
In the drawings, identification numeral 102 indicates conductive regions, such as source/drain, and al illustrates the minimum size of the contact hole defined with recent photo devices, being approximately between 0.16 and 0.18 xcexcm, and desirably, 0.17 xcexcm.
Subsequently, photoresist is applied on the Anti-Reflective Coating layer 106 and exposure and development processes are performed to form a photoresist (PR) pattern 108 exposing a part corresponding to the conductive regions 102. In order to minimize the size of the part exposing the part corresponding to the conductive regions on the photoresist pattern, the photoresist pattern is made by using a thermal flow process.
Referring to FIG. 1B, the Anti-Reflective Coating layer is removed by a first dry etch process 120 using the photoresist pattern PR 108 as a mask. The first dry etch process is performed by using a mixed gas comprising CH4, Ar and O2 as an etching gas, wherein the Anti-Reflective Coating layer exposed by the photoresist pattern PR 108 is removed by chemical reaction with the mixed gas. The Anti-Reflective Coating layer 107 remains after the first dry etch process. The remaining Anti-Reflective Coating layer 107 has a vertical profile.
Referring to FIGS. 1C and 2, the insulating layer 104 is removed in accordance with a second dry etch process 122 using the photoresist pattern PR 108 as a mask, thereby forming a contact hole 130. The second dry etch process 122 is performed by using a mixed gas comprising C4H8, CH2F2 and Ar as etching gas. The insulating layer exposed by the photoresist pattern (PR) 108 is removed by chemical reaction with the mixed gas.
The contact hole 130 has a size the same as that of the contact hole originally to be defined, that is, between 0.16 and 0.18 xcexcm, and desirably 0.17 xcexcm.
The insulating layer 105 remains after the second dry etch process 122.
Referring to FIG. 1D, the photoresist pattern (PR) 108 and the remaining Anti-Reflective Coating layer 107 are removed by a conventional process, such as polishing.
Referring to FIG. 1E, a metal layer is formed on the resulting structure by sputtering metal to cover the contact hole 130 and a pattern etch process is performed on the metal layer, thereby forming a bit line 132, as shown.
The following table 1 shows wafer CD values according to the conventional method, wherein xe2x80x98Cxe2x80x99 indicates the center of the wafer, xe2x80x98Lxe2x80x99 left of the center C, xe2x80x98Rxe2x80x99 right of the center C, xe2x80x98Txe2x80x99 top, xe2x80x98Bxe2x80x99 bottom, xe2x80x98LTxe2x80x99 is at a 45xc2x0 angle between the left L and the top T, xe2x80x98RTxe2x80x99 is at a 45xc2x0 angle between the right R and the top T, xe2x80x98RBxe2x80x99 is at a 45xc2x0 angle between the right R and the bottom B and xe2x80x98LBxe2x80x99 is at a 45xc2x0 angle between the left L and the bottom B.
According to the conventional method, the contact hole having a dimension between 0.16 and 0.18 xcexcm is obtained. However, it is difficult to fabricate a contact hole below 0.14 xcexcm. A further problem is encountered in lowering the Critical Dimension CD uniformity of a wafer, since the reflow process is performed on the photoresist pattern.
Therefore, the present invention has been made to solve the above-mentioned problems and the object of the present invention is to provide a method of fabricating semiconductor devices capable of controlling the size of contact hole for bit line formation below 0.14 xcexcm.
In order to accomplish the above object, the present invention comprises the steps of: forming an insulating layer and an Anti-Reflective Coating layer on a substrate, the substrate including conductive regions; forming a photoresist pattern opening over the conductive regions on the Anti-Reflective Coating layer; etching the Anti-Reflective Coating layer in accordance with a first dry etch process using a mixed gas of SO2 and He and employing the photoresist pattern as an etch mask and at the same time, forming a polymer sidewall by attaching polymer generated in the first dry etch process to the sides of the remaining Anti-Reflective Coating layer; forming a contact hole by removing the insulating layer in accordance with a second dry etch process employing the photoresist pattern and the polymer sidewall as an etch mask; and removing the photoresist pattern, the remaining Anti-Reflective Coating layer and the polymer sidewall.